535 search results - page 104 / 107 » The Cache Performance and Optimizations of Blocked Algorithm... |
FPGA
2003
ACM
15 years 4 months ago
2003
ACM
We present a pipelining-aware router for FPGAs. The problem of routing pipelined signals is different from the conventional FPGA routing problem. For example, the two terminal N-D...
CODES
2008
IEEE
15 years 6 months ago
2008
IEEE
Instruction set extensions (ISEs) can accelerate embedded processor performance. Many algorithms for ISE generation have shown good potential; some of them have recently been expa...
105
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HPCA
1998
IEEE
15 years 3 months ago
1998
IEEE
This paper describes PRISM, a distributed sharedmemory architecture that relies on a tightly integrated hardware and operating system design for scalable and reliable performance....
CGO
2006
IEEE
15 years 3 months ago
2006
IEEE
Modern computer systems are called on to deal with billions of events every second, whether they are instructions executed, memory locations accessed, or packets forwarded. This p...
118
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PVLDB
2010
14 years 10 months ago
2010
Recently, there has been increasing interest in extending relational query processing to include data obtained from unstructured sources. A common approach is to use stand-alone I...