535 search results - page 16 / 107 » The Cache Performance and Optimizations of Blocked Algorithm... |
DSD
2010
IEEE
14 years 12 months ago
2010
IEEE
Abstract—Resizable caches can trade-off capacity for access speed to dynamically match the needs of the workload. In Simultaneous Multi-Threaded (SMT) cores, the caching needs ca...
ISCAS
2007
IEEE
15 years 6 months ago
2007
IEEE
-- In interconnect-dominated designs, the ability to minimize layout-induced parasitic effects is crucial for rapid design closure. Deep sub-micron effects and ubiquitous interfere...
105
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SIGARCH
2008
14 years 11 months ago
2008
1 This paper presents a simple but effective method to reduce on-chip access latency and improve core isolation in CMP Non-Uniform Cache Architectures (NUCA). The paper introduces ...
117
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ACMMSP
2005
ACM
15 years 5 months ago
2005
ACM
In this work we investigate the impact of evolving memory system features, such as large on-chip caches, automatic prefetch, and the growing distance to main memory on 3D stencil ...
MICRO
1998
IEEE
15 years 3 months ago
1998
IEEE
The fill unit is the structure which collects blocks of instructions and combines them into multi-block segments for storage in a trace cache. In this paper, we expand the role of...