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GLVLSI
2008
IEEE
112views VLSI» more  GLVLSI 2008»
15 years 6 months ago
Instruction cache leakage reduction by changing register operands and using asymmetric sram cells
Share of leakage in cache memories is increasing with technology scaling. Studies show that most stored bits in instruction caches are zero, and hence, asymmetric SRAM cells which...
Maziar Goudarzi, Tohru Ishihara
MFCS
2010
Springer
14 years 10 months ago
Evaluating Non-square Sparse Bilinear Forms on Multiple Vector Pairs in the I/O-Model
We consider evaluating one bilinear form defined by a sparse Ny × Nx matrix A having h entries on w pairs of vectors The model of computation is the semiring I/O-model with main ...
Gero Greiner, Riko Jacob
AC
1997
Springer
15 years 4 months ago
Recent Developments in the Design of Conventional Cryptographic Algorithms
Abstract. This paper examines proposals for three cryptographic primitives: block ciphers, stream ciphers, and hash functions. It provides an overview of the design principles of a...
Bart Preneel, Vincent Rijmen, Antoon Bosselaers
ICS
2003
Tsinghua U.
15 years 5 months ago
Estimating cache misses and locality using stack distances
Cache behavior modeling is an important part of modern optimizing compilers. In this paper we present a method to estimate the number of cache misses, at compile time, using a mac...
Calin Cascaval, David A. Padua
ICASSP
2009
IEEE
15 years 6 months ago
Microarray classification using block diagonal linear discriminant analysis with embedded feature selection
In this paper, block diagonal linear discriminant analysis (BDLDA) is improved and applied to gene expression data. BDLDA is a classification tool with embedded feature selection...
Lingyan Sheng, Roger Pique-Regi, Shahab Asgharzade...