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DAC
2009
ACM
15 years 6 months ago
Clock skew optimization via wiresizing for timing sign-off covering all process corners
Manufacturing process variability impacts the performance of synchronous logic circuits by means of its effect on both clock network and functional block delays. Typically, varia...
Sari Onaissi, Khaled R. Heloue, Farid N. Najm
AES
2000
Springer
117views Cryptology» more  AES 2000»
15 years 4 months ago
A Comparison of AES Candidates on the Alpha 21264
We compare the five candidates for the Advanced Encryption Standard based on their performance on the Alpha 21264, a 64-bit superscalar processor. There are several new features o...
Richard Weiss, Nathan L. Binkert
COMSWARE
2007
IEEE
15 years 6 months ago
Leveraging MAC-layer information for single-hop wireless transport in the Cache and Forward Architecture of the Future Internet
— Cache and Forward (CNF) Architecture is a novel architecture aimed at delivering content efficiently to potentially large number of intermittently connected mobile hosts. It us...
Sumathi Gopal, Sanjoy Paul, Dipankar Raychaudhuri
EWC
2006
120views more  EWC 2006»
14 years 11 months ago
A comparison of two optimization methods for mesh quality improvement
We compare inexact Newton and block coordinate descent optimization methods for improving the quality of a mesh by repositioning the vertices, where the overall quality is measure...
Lori Freitag Diachin, Patrick M. Knupp, Todd S. Mu...
AMC
2006
80views more  AMC 2006»
14 years 12 months ago
Parallel preconditioned conjugate gradient optimization of the Rayleigh quotient for the solution of sparse eigenproblems
A parallel algorithm based on the multidimensional minimization of the Rayleigh quotient is proposed to evaluate the leftmost eigenpairs of the generalized symmetric positive defi...
Luca Bergamaschi, Angeles Martinez, Giorgio Pini