535 search results - page 79 / 107 » The Cache Performance and Optimizations of Blocked Algorithm... |
101
Voted
CODES
2006
IEEE
15 years 8 months ago
2006
IEEE
When designing a System-on-Chip (SoC) using a Networkon-Chip (NoC), silicon area and power consumption are two key elements to optimize. A dominant part of the NoC area and power ...
119
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CASES
2010
ACM
14 years 12 months ago
2010
ACM
We present a fine-grain dynamic instruction placement algorithm for small L0 scratch-pad memories (spms), whose unit of transfer can be an individual instruction. Our algorithm ca...
117
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SIGMETRICS
2005
ACM
15 years 7 months ago
2005
ACM
The running time of many applications is dominated by the cost of memory operations. To optimize such applications for a given platform, it is necessary to have a detailed knowled...
103
Voted
ICIP
2003
IEEE
16 years 3 months ago
2003
IEEE
In this paper, we propose a novel rate-distortion (R-D) optimized disparity based coding scheme for stereo images. This new scheme efficiently integrates the coding of the dispari...
122
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ICPP
2005
IEEE
15 years 7 months ago
2005
IEEE
In this paper we introduce a new algorithm for computing near optimal schedules for task graph problems. In contrast to conventional approaches for solving those scheduling proble...