148 search results - page 10 / 30 » The Challenges of Hardware Synthesis from C-Like Languages |
100
Voted
ICCAD
2010
IEEE
14 years 10 months ago
2010
IEEE
Craig Interpolation is a state-of-the-art technique for logic synthesis and verification, based on Boolean Satisfiability (SAT). Leveraging the efficacy of SAT algorithms, Craig In...
90
Voted
ASPDAC
2005
ACM
15 years 6 months ago
2005
ACM
- Many high-level description languages, such as C/C++ or Java, lack the capability to specify the bitwidth information for variables and operations. Synthesis from these specifica...
DATE
2008
IEEE
15 years 6 months ago
2008
IEEE
This paper describes an implementation language and synthesis system for automatically generating latency insensitive synchronous digital designs. These designs decouple behaviora...
95
Voted
FPGA
2010
ACM
15 years 9 months ago
2010
ACM
d hardware design from behavior-level abstraction has drawn wide interest in FPGA-based acceleration and configurable computing research field. However, for many high-level progra...
ICCAD
2005
IEEE
15 years 9 months ago
2005
IEEE
—Existing ASIPs (application-specific instruction-set processors) and compiler-based co-processor synthesis approaches meet the increasing performance requirements of embedded ap...