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» The Challenges of Hardware Synthesis from C-Like Languages
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ISPD
2012
ACM
252views Hardware» more  ISPD 2012»
13 years 5 months ago
Towards layout-friendly high-level synthesis
There are two prominent problems with technology scaling: increasing design complexity and more challenges with interconnect design, including routability. High-level synthesis ha...
Jason Cong, Bin Liu 0006, Guojie Luo, Raghu Prabha...
ICCAD
2006
IEEE
131views Hardware» more  ICCAD 2006»
15 years 7 months ago
High-level synthesis challenges and solutions for a dynamically reconfigurable processor
A dynamically reconfigurable processor (DRP) is designed to achieve high area efficiency by switching reconfigurable data paths dynamically. Our DRP architecture has a stand alone...
Takao Toi, Noritsugu Nakamura, Yoshinosuke Kato, T...
ICCAD
2004
IEEE
113views Hardware» more  ICCAD 2004»
15 years 7 months ago
High-level synthesis: an essential ingredient for designing complex ASICs
It is common wisdom that synthesizing hardware from higher-level descriptions than Verilog will incur a performance penalty. The case study here shows that this need not be the ca...
Arvind, Rishiyur S. Nikhil, Daniel L. Rosenband, N...
ARC
2008
Springer
104views Hardware» more  ARC 2008»
15 years 2 days ago
PARO: Synthesis of Hardware Accelerators for Multi-Dimensional Dataflow-Intensive Applications
Abstract. In this paper, we present the PARO design tool for the automated hardware synthesis of massively parallel embedded architectures for given dataflow dominant applications....
Frank Hannig, Holger Ruckdeschel, Hritam Dutta, J&...
ASPDAC
2007
ACM
98views Hardware» more  ASPDAC 2007»
15 years 2 months ago
Efficient Automata-Based Assertion-Checker Synthesis of SEREs for Hardware Emulation
In this paper, we present a method for generating checker circuits from sequential-extended regular expressions (SEREs). Such sequences form the core of increasingly-used Assertion...
Marc Boule, Zeljko Zilic