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» The Chimaera reconfigurable functional unit
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KES
2005
Springer
15 years 3 months ago
Reconfigurable Power-Aware Scalable Booth Multiplier
Abstract. An energy-efficient power-aware design is highly desirable for digital signal processing functions that encounter a wide diversity of operating scenarios in battery-power...
Hanho Lee
DATE
2006
IEEE
195views Hardware» more  DATE 2006»
15 years 3 months ago
Application specific instruction processor based implementation of a GNSS receiver on an FPGA
In this paper the concept of a reconfigurable hardware macro to be used as a generic building block in lowpower, low-cost SoC for multioperable GNSS positioning is described, feat...
Götz Kappen, Tobias G. Noll
IPPS
2000
IEEE
15 years 1 months ago
Augmenting Modern Superscalar Architectures with Configurable Extended Instructions
The instruction sets of general-purpose microprocessors are designed to offer good performance across a wide range of programs. The size and complexity of the instruction sets, how...
Xianfeng Zhou, Margaret Martonosi
ARC
2007
Springer
150views Hardware» more  ARC 2007»
15 years 1 months ago
MT-ADRES: Multithreading on Coarse-Grained Reconfigurable Architecture
The coarse-grained reconfigurable architecture ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) and its compiler offer high instruction-level parallelism (ILP)...
Kehuai Wu, Andreas Kanstein, Jan Madsen, Mladen Be...
ICCD
2006
IEEE
134views Hardware» more  ICCD 2006»
15 years 3 months ago
Automated Design of Microfluidics-Based Biochips: Connecting Biochemistry to Electronics CAD
Microfluidics-based biochips offer exciting possibilities for highthroughput sequencing, parallel immunoassays, blood chemistry for clinical diagnostics, DNA sequencing, and envir...
Krishnendu Chakrabarty