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IEEEPACT
2006
IEEE
16 years 8 days ago
Overlapping dependent loads with addressless preload
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
Zhen Yang, Xudong Shi, Feiqi Su, Jih-Kwon Peir
IPTPS
2005
Springer
15 years 11 months ago
Evaluating DHT-Based Service Placement for Stream-Based Overlays
Stream-based overlay networks (SBONs) are one approach to implementing large-scale stream processing systems. A fundamental consideration in an SBON is that of service placement, ...
Peter R. Pietzuch, Jeffrey Shneidman, Jonathan Led...
FPGA
2004
ACM
119views FPGA» more  FPGA 2004»
15 years 11 months ago
A quantitative analysis of the speedup factors of FPGAs over processors
The speedup over a microprocessor that can be achieved by implementing some programs on an FPGA has been extensively reported. This paper presents an analysis, both quantitative a...
Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vis...
TEI
2010
ACM
130views Hardware» more  TEI 2010»
15 years 11 months ago
Creating with cobots
In the world of interactive art, very few pieces have a permanent, physical outcome. In response to this observation, the author developed two “cobots”, or collaborative robot...
Christian D. Cerrito
ISCA
2002
IEEE
93views Hardware» more  ISCA 2002»
15 years 11 months ago
Transient-Fault Recovery Using Simultaneous Multithreading
We propose a scheme for transient-fault recovery called Simultaneously and Redundantly Threaded processors with Recovery (SRTR) that enhances a previously proposed scheme for tran...
T. N. Vijaykumar, Irith Pomeranz, Karl Cheng