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ISCA
2006
IEEE
187views Hardware» more  ISCA 2006»
15 years 11 months ago
A Case for MLP-Aware Cache Replacement
Performance loss due to long-latency memory accesses can be reduced by servicing multiple memory accesses concurrently. The notion of generating and servicing long-latency cache m...
Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu,...
SIGCOMM
2006
ACM
15 years 11 months ago
SybilGuard: defending against sybil attacks via social networks
Peer-to-peer and other decentralized, distributed systems are known to be particularly vulnerable to sybil attacks. In a sybil attack, a malicious user obtains multiple fake ident...
Haifeng Yu, Michael Kaminsky, Phillip B. Gibbons, ...
SIGIR
2006
ACM
15 years 11 months ago
AggregateRank: bringing order to web sites
Since the website is one of the most important organizational structures of the Web, how to effectively rank websites has been essential to many Web applications, such as Web sear...
Guang Feng, Tie-Yan Liu, Ying Wang, Ying Bao, Zhim...
FDL
2005
IEEE
15 years 10 months ago
Incorporating SystemC in Analog/Mixed-Signal Design Flow
In today’s flows, there is still a gap between system level description and hardware implementation, especially for analog/RF building blocks. SystemC-AMS or co-simulations have...
Patrick Birrer, Walter Hartong
INFOCOM
2005
IEEE
15 years 10 months ago
On the maximal throughput of networks with finite buffers and its application to buffered crossbars
— The advent of packet networks has motivated many researchers to study the performance of networks of queues in the last decade or two. However, most of the previous work assume...
Paolo Giaccone, Emilio Leonardi, Devavrat Shah