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ITC
1998
IEEE
95views Hardware» more  ITC 1998»
15 years 6 months ago
Native mode functional test generation for processors with applications to self test and design validation
New methodologies based on functional testing and built-in self-test can narrow the gap between necessary solutions and existing techniques for processor validation and testing. W...
Jian Shen, Jacob A. Abraham
APSEC
2010
IEEE
14 years 9 months ago
Quantitative Analysis of Best Practices Models in the Software Domain
Organizations are adopting multiple best practices models to improve overall performance. Their objective is to capture the cumulative added value of each model into one single env...
André L. Ferreira, Ricardo Jorge Machado, M...
ISSTA
2004
ACM
15 years 7 months ago
Test input generation with java PathFinder
We show how model checking and symbolic execution can be used to generate test inputs to achieve structural coverage of code that manipulates complex data structures. We focus on ...
Willem Visser, Corina S. Pasareanu, Sarfraz Khursh...
ICCD
2006
IEEE
116views Hardware» more  ICCD 2006»
15 years 10 months ago
RTL Scan Design for Skewed-Load At-speed Test under Power Constraints
This paper discusses an automated method to build scan chains at the register-transfer level (RTL) for powerconstrained at-speed testing. By analyzing a circuit at the RTL, where ...
Ho Fai Ko, Nicola Nicolici
IROS
2009
IEEE
163views Robotics» more  IROS 2009»
15 years 8 months ago
On the performance of random linear projections for sampling-based motion planning
— Sampling-based motion planners are often used to solve very high-dimensional planning problems. Many recent algorithms use projections of the state space to estimate properties...
Ioan Alexandru Sucan, Lydia E. Kavraki