175 search results - page 33 / 35 » The Complexity of Model Checking Higher-Order Fixpoint Logic |
DATE
2009
IEEE
15 years 4 months ago
2009
IEEE
Abstract—Addressing both standby and active power is a major challenge in developing System-on-Chip designs for batterypowered products. Powering off sections of logic or memorie...
DAC
2009
ACM
15 years 10 months ago
2009
ACM
Continuously shrinking feature sizes result in an increasing susceptibility of circuits to transient faults, e.g. due to environmental radiation. Approaches to implement fault tol...
CADE
2008
Springer
15 years 10 months ago
2008
Springer
We propose a procedure for automated implicit inductive theorem proving for equational specifications made of rewrite rules with conditions and constraints. The constraints are int...
ICSE
2008
IEEE-ACM
15 years 9 months ago
2008
IEEE-ACM
This paper examines the suitability and use of runtime verification as means for monitoring security protocols and their properties. In particular, we employ the runtime verificat...
78
Voted
GLVLSI
2009
IEEE
15 years 4 months ago
2009
IEEE
The sequential depth determines the completeness of bounded model checking in design verification. Recently, a SATbased method is proposed to compute the sequential depth of a de...