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» The Concurrent Matching Switch Architecture
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CCR
2006
122views more  CCR 2006»
13 years 6 months ago
Low complexity, stable scheduling algorithms for networks of input queued switches with no or very low speed-up
The delay and throughput characteristics of a packet switch depend mainly on the queueing scheme and the scheduling algorithm deployed at the switch. Early research on scheduling ...
Claus Bauer
NAS
2007
IEEE
14 years 15 days ago
An Object-based Storage Controller Based on Switch Fabric
Object-based Storage Controller (OSC) plays a decisive role in the performance of the whole Object-based Storage Systems (OBSS). A new OSC based on switch fabric proposed in this ...
Shuibing He, Dan Feng
GLOBECOM
2006
IEEE
14 years 8 days ago
Multicast Support for a Storage Area Network Switch
— Efficient support of multicast traffic in Storage Area Networks (SANs) enables applications such as remote data replication and distributed multimedia systems, in which a ser...
Andrea Bianco, Paolo Giaccone, Enrico Maria Giraud...
ISLPED
2005
ACM
85views Hardware» more  ISLPED 2005»
13 years 11 months ago
A low-power crossroad switch architecture and its core placement for network-on-chip
As the number of cores on a chip increases, power consumed by the communication structures takes significant portion of the overall power-budget. The individual components of the...
Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen
FTCS
1994
140views more  FTCS 1994»
13 years 7 months ago
Concurrent Error Detection in Self-Timed VLSI
This paper examines architectural techniques for providing concurrent error detection in self-timed VLSI pipelines. Signal pairs from Differential Cascode Voltage Switch Logic are...
David A. Rennels, Hyeongil Kim