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IPPS
2006
IEEE
15 years 10 months ago
Analysis of checksum-based execution schemes for pipelined processors
The performance requirements for contemporary microprocessors are increasing as rapidly as their number of applications grows. By accelerating the clock, performance can be gained...
Bernhard Fechner
ISCA
2006
IEEE
137views Hardware» more  ISCA 2006»
15 years 10 months ago
Multiple Instruction Stream Processor
Microprocessor design is undergoing a major paradigm shift towards multi-core designs, in anticipation that future performance gains will come from exploiting threadlevel parallel...
Richard A. Hankins, Gautham N. Chinya, Jamison D. ...
122
Voted
ISM
2006
IEEE
81views Multimedia» more  ISM 2006»
15 years 10 months ago
Water Jets as Pixels: Water Fountains as Both Sensors and Displays
We propose a hydraulic user interface consisting of an array of spray jets and the appropriate fluid sensing and fluid flow control systems for each jet, so that the device fun...
Steve Mann, Michael Georgas, Ryan E. Janzen
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
15 years 10 months ago
ASR: Adaptive Selective Replication for CMP Caches
The large working sets of commercial and scientific workloads stress the L2 caches of Chip Multiprocessors (CMPs). Some CMPs use a shared L2 cache to maximize the on-chip cache c...
Bradford M. Beckmann, Michael R. Marty, David A. W...
RTSS
2006
IEEE
15 years 9 months ago
Tightening the Bounds on Feasible Preemption Points
Caches have become invaluable for higher-end architectures to hide, in part, the increasing gap between processor speed and memory access times. While the effect of caches on timi...
Harini Ramaprasad, Frank Mueller
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