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DFT
2007
IEEE
103views VLSI» more  DFT 2007»
15 years 6 months ago
Reliable Network-on-Chip Using a Low Cost Unequal Error Protection Code
The network-on-chip (NoC) paradigm is seen as a way of facilitating the integration of a large number of computational and storage blocks on a chip to meet several performance and...
Avijit Dutta, Nur A. Touba
IEEEPACT
2002
IEEE
15 years 4 months ago
Cost Effective Memory Dependence Prediction using Speculation Levels and Color Sets
Memory dependence prediction allows out-of-order issue processors to achieve high degrees of instruction level parallelism by issuing load instructions at the earliest time withou...
Soner Önder
ICCBR
2003
Springer
15 years 5 months ago
Using Case-Based Reasoning to Overcome High Computing Cost Interactive Simulations
Abstract. This paper describes an innovative usage of Case-Based Reasoning to reduce the high computing cost derived from running large interactive simulation scenarios within the ...
Javier Vázquez-Salceda, Miquel Sànch...
BMCBI
2006
139views more  BMCBI 2006»
14 years 11 months ago
Improvement in accuracy of multiple sequence alignment using novel group-to-group sequence alignment algorithm with piecewise li
Background: Multiple sequence alignment (MSA) is a useful tool in bioinformatics. Although many MSA algorithms have been developed, there is still room for improvement in accuracy...
Shinsuke Yamada, Osamu Gotoh, Hayato Yamana
DATE
2005
IEEE
224views Hardware» more  DATE 2005»
15 years 5 months ago
Low-Cost Multi-Gigahertz Test Systems Using CMOS FPGAs and PECL
This paper describes two research projects that develop new low-cost techniques for testing devices with multiple high-speed (2 to 5 Gbps) signals. Each project uses commercially ...
David C. Keezer, C. Gray, A. M. Majid, N. Taher