Abstract— Process variations make at-speed testing significantly more difficult. They cause subtle delay changes that are distributed rather than the localized nature of a trad...
Vladimir Zolotov, Jinjun Xiong, Hanif Fatemi, Chan...
The interconnection delay of pre-fabricated design style dominates circuit delay due to the heavily downstream capacitance. Buffer insertion is a widely used technique to split o...
—In this paper we propose a model to compute an upper bound for the maximum network size in mobile ad-hoc networks. Our model is based on the foundation that for a unicast route ...
Michael Pascoe, Javier Gomez, Victor Rangel, Migue...
The problem of interest is to characterize to what extent nodes independently following certain transmission schedules can be hijacked to relay flows of information packets. Info...
—Circuit-switched networks can significantly lower the communication latency between processor cores, when compared to packet-switched networks, since once circuits are set up, ...
Natalie D. Enright Jerger, Li-Shiuan Peh, Mikko H....