1691 search results - page 161 / 339 » The Delayed k-Server Problem |
133
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VTS
1996
IEEE
15 years 8 months ago
1996
IEEE
In this paper we investigate optimal voltage testing approaches for physically-based faults in CMOS circuits. We describe the general nature of the problem and then focus on two f...
123
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CHI
1996
ACM
15 years 8 months ago
1996
ACM
: This paper describes techniques for maximizing the efficient use of small screen space by combining delayed response with semi-transparency of control objects ("widgets"...
149
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DAC
2010
ACM
15 years 8 months ago
2010
ACM
The identification of speedpaths is required for post-silicon (PS) timing validation, and it is currently becoming timeconsuming due to manufacturing variations. In this paper we...
136
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DATE
2004
IEEE
15 years 7 months ago
2004
IEEE
Latency-insensitive systems were recently proposed by Carloni et al. as a correct-by-construction methodology for single-clock system-on-a-chip (SoC) design using predesigned IP b...
126
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CHES
2006
Springer
15 years 7 months ago
2006
Springer
In recent years, some countermeasures against Differential Power Analysis (DPA) at the logic level have been proposed. At CHES 2005 conference, Popp and Mangard proposed a new coun...