The throughput of a multiple-pipelined processor suffers due to lack of sufficient instructions to make multiple pipelines busy and due to delays associated with pipeline depende...
In the nanometer manufacturing region, process variation causes significant uncertainty for circuit performance verification. Statistical static timing analysis (SSTA) is thus dev...
Designers aim at fast but low-power consuming integrated circuits. Since high processing speed always comes with high energy demands, the literature provides several ways to reduc...
In [Dague, 1993], a formal system ROM(K) involving four relations has been defined to reason with relative orders of magnitude. In this paper, problems of introducing quantitative...
We study diagnosis of segments on speedpaths that fail the timing constraint at the post-silicon stage due to manufacturing variations. We propose a formal procedure that is appli...