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» The Design, Implementation, and Evaluation of Jade
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VLSID
2005
IEEE
158views VLSI» more  VLSID 2005»
15 years 10 months ago
Algorithmic Implementation of Low-Power High Performance FIR Filtering IP Cores
This paper presents two schemes for the implementation of high performance and low power FIR filtering Intellectual Property (IP) cores. Low power is achieved through the utilizat...
C. H. Wang, Ahmet T. Erdogan, Tughrul Arslan
DATE
2007
IEEE
97views Hardware» more  DATE 2007»
15 years 4 months ago
Systematic comparison between the asynchronous and the multi-synchronous implementations of a network on chip architecture
In this paper we present a systematic comparison between two different implementations of a distributed Network on Chip: fully asynchronous and multi-synchronous. The NoC architec...
Abbas Sheibanyrad, Ivan Miro Panades, Alain Greine...
APCSAC
2000
IEEE
15 years 2 months ago
Cost/Performance Tradeoff of n-Select Square Root Implementations
Hardware square-root units require large numbers of gates even for iterative implementations. In this paper, we present four low-cost high-performance fullypipelined n-select impl...
Wanming Chu, Yamin Li
EUROMICRO
2006
IEEE
15 years 3 months ago
Using WS-BPEL to Implement Software Fault Tolerance for Web Services
One area of the web services architecture yet to be standardised is that of fault tolerance for services. At the same time, WS-BPEL is moving from a de facto standard to an OASIS ...
Glen Dobson
ICALT
2006
IEEE
15 years 3 months ago
Tuning IMS LD for Implementing a Collaborative Lifelong Learning Scenario
This paper describes an approach for modeling and implementing a collaborative learning situation, which is part of a real lifelong learning scenario in astronomy. We adopt and sl...
Davinia Hernández Leo, Eloy D. Villasclaras...