5005 search results - page 125 / 1001 » The Design and Analysis of Parallel Algorithms |
90
Voted
ICCAD
1994
IEEE
15 years 4 months ago
1994
IEEE
For a logic design with level-sensitive latches, we need to validate timing signal paths which may flush through several latches. We developed efficient algorithms based on the mo...
109
click to vote
IPPS
2009
IEEE
15 years 7 months ago
2009
IEEE
Many image and signal processing kernels can be optimized for performance consuming a reasonable area by doing loops parallelization with extensive use of pipelining. This paper p...
111
Voted
IPPS
2003
IEEE
15 years 6 months ago
2003
IEEE
We present a method for the automatic generation of oligonucleotide probe sets for DNA microarrays. This approach is well suited particularly for specificity evaluation of design...
IPPS
2006
IEEE
15 years 6 months ago
2006
IEEE
The RTSJ memory model propose a mechanism based on a scope three containing all region-stacks in the system and a reference-counter collector. In order to avoid reference cycles a...
118
click to vote
IEEEPACT
2006
IEEE
15 years 6 months ago
2006
IEEE
Transactional memory is an attractive design concept for scalable multiprocessors because it offers efficient lock-free synchronization and greatly simplifies parallel software....