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ISCAS
2007
IEEE
141views Hardware» more  ISCAS 2007»
16 years 15 days ago
Towards a GBit/s Programmable Decoder for LDPC Convolutional Codes
Abstract— We analyze the decoding algorithm for regular timeinvariant LDPC convolutional codes as a 3D signal processing scheme and derive several parallelization concepts, which...
Emil Matús, Marcos B. S. Tavares, Marcel Bi...
PODC
2003
ACM
15 years 11 months ago
Adapting to a reliable network path
We consider the model of unreliable network links, where at each time unit a link might be either up or down. We consider two related problems. The first, establishing end to end...
Baruch Awerbuch, Yishay Mansour
ISORC
2000
IEEE
15 years 10 months ago
Experimentation in CPU Control with Real-Time Java
This paper describes experiences in using an O.O. language (Java) in designing, prototyping and evaluating a CPU manager. QoS Animator facilitates the execution of object oriented...
Gerasimos Xydas, Jerome Tassel
IPPS
1999
IEEE
15 years 10 months ago
Fully-Scalable Fault-Tolerant Simulations for BSP and CGM
In this paper we consider general simulations of algorithms designed for fully operational BSP and CGM machines on machines with faulty processors. The faults are deterministic (i...
Sung-Ryul Kim, Kunsoo Park
ICDCS
1994
IEEE
15 years 10 months ago
Implementation of Process Migration in Amoeba
The design of a process migration mechanism for the Amoeba distributed operating system is described. The primary motivation for this implementation is to carry out experimental a...
Chris Steketee, Weiping Zhu, Philip Moseley