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» The Design and Implementation of a Certifying Compiler
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MP
1998
117views more  MP 1998»
14 years 11 months ago
The node capacitated graph partitioning problem: A computational study
In this paper we consider the problem of ^-partitioning the nodes of a graph with capacity restrictions on the sum of the node weights in each subset of the partition, and the obje...
Carlos Eduardo Ferreira, Alexander Martin, C. Carv...
CASES
2007
ACM
15 years 3 months ago
Performance-driven syntax-directed synthesis of asynchronous processors
The development of robust and efficient synthesis tools is important if asynchronous design is to gain more widespread acceptance. Syntax-directed translation is a powerful synthe...
Luis A. Plana, Doug A. Edwards, Sam Taylor, Luis A...
DAC
2003
ACM
16 years 24 days ago
Clock-tree power optimization based on RTL clock-gating
As power consumption of the clock tree in modern VLSI designs tends to dominate, measures must be taken to keep it under control. This paper introduces an approach for reducing cl...
Monica Donno, Alessandro Ivaldi, Luca Benini, Enri...
FCCM
2002
IEEE
133views VLSI» more  FCCM 2002»
15 years 4 months ago
Reconfigurable Shape-Adaptive Template Matching Architectures
This paper presents three reconfigurable computing approaches for a Shape-Adaptive Template Matching (SA-TM) method to retrieve arbitrarily shaped objects within images or video f...
Jörn Gause, Peter Y. K. Cheung, Wayne Luk
TCAD
2011
14 years 6 months ago
High-Level Synthesis for FPGAs: From Prototyping to Deployment
—Escalating system-on-chip design complexity is the design community to raise the level of abstraction beyond register transfer level. Despite the unsuccessful adoptions of early...
Jason Cong, Bin Liu, Stephen Neuendorffer, Juanjo ...