225 search results - page 13 / 45 » The Design and Optimization of SOC Test Solutions |
ICCAD
2001
IEEE
15 years 6 months ago
2001
IEEE
: This paper describes ASF, a novel cell-level analog synthesis framework that can size and bias a given circuit topology subject to a set of performance objectives and a manufactu...
CEC
2009
IEEE
15 years 4 months ago
2009
IEEE
— In this paper, the performance assessment of the hybrid Archive-based Micro Genetic Algorithm (AMGA) on a set of bound-constrained synthetic test problems is reported. The hybr...
FMCAD
2007
Springer
15 years 1 months ago
2007
Springer
In today's SoC design cycles, debugging is one of the most time consuming manual tasks. CAD solutions strive to reduce the inefficiency of debugging by identifying error sourc...
ISDA
2008
IEEE
15 years 3 months ago
2008
IEEE
Both simulated annealing (SA) and the genetic algorithms (GA) are stochastic and derivative-free optimization technique. SA operates on one solution at a time, while the GA mainta...
ASPDAC
2009
ACM
15 years 4 months ago
2009
ACM
Three-dimensional stacking of silicon layers is emerging as a promising solution to handle the design complexity and heterogeneity of Systems on Chips (SoCs). Networks on Chips (N...