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» The Design and Optimization of SOC Test Solutions
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ICCAD
1995
IEEE
94views Hardware» more  ICCAD 1995»
15 years 5 months ago
Test register insertion with minimum hardware cost
Implementing a built-in self-test by a "test per clock" scheme offers advantages concerning fault coverage, detection of delay faults, and test application time. Such a ...
Albrecht P. Stroele, Hans-Joachim Wunderlich
CEC
2010
IEEE
15 years 2 months ago
Elitist Artificial Bee Colony for constrained real-parameter optimization
Abstract-- A novel algorithm to solve constrained realparameter optimization problems, based on the Artificial Bee Colony algorithm is introduced in this paper. The operators used ...
Efrén Mezura-Montes, Ramiro Ernesto Velez-K...
CP
2009
Springer
15 years 8 months ago
A Hybrid Constraint Model for the Routing and Wavelength Assignment Problem
In this paper we present a hybrid model for the demand acceptance variant of the routing and wavelength assignment problem in directed networks, an important benchmark problem in o...
Helmut Simonis
CEC
2007
IEEE
15 years 7 months ago
Light beam search based multi-objective optimization using evolutionary algorithms
Abstract— For the past decade or so, evolutionary multiobjective optimization (EMO) methodologies have earned wide popularity for solving complex practical optimization problems,...
Kalyanmoy Deb, Abhay Kumar
DDECS
2007
IEEE
201views Hardware» more  DDECS 2007»
15 years 7 months ago
Built in Defect Prognosis for Embedded Memories
: As scan compression replaces the traditional scan it is important to understand how it works with power. DFT MAX represents one of the two primary scan compression solutions used...
Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskaran...