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» The Design and Optimization of SOC Test Solutions
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JEA
2006
90views more  JEA 2006»
14 years 9 months ago
Heuristics for estimating contact area of supports in layered manufacturing
Layered Manufacturing is a technology that allows physical prototypes of three-dimensional models to be built directly from their digital representation, as a stack of two-dimensi...
Ivaylo Ilinkin, Ravi Janardan, Michiel H. M. Smid,...
PLDI
1994
ACM
15 years 1 months ago
Memory Access Coalescing: A technique for Eliminating Redundant memory Accesses
As microprocessor speeds increase, memory bandwidth is increasing y the performance bottleneck for microprocessors. This has occurred because innovation and technological improvem...
Jack W. Davidson, Sanjay Jinturkar
GLVLSI
2009
IEEE
103views VLSI» more  GLVLSI 2009»
15 years 4 months ago
Enhancing bug hunting using high-level symbolic simulation
The miniaturization of transistors in recent technology nodes requires tremendous back-end tuning and optimizations, making bug fixing at later design stages more expensive. Ther...
Hong-Zu Chou, I-Hui Lin, Ching-Sung Yang, Kai-Hui ...
ISCA
2008
IEEE
132views Hardware» more  ISCA 2008»
15 years 3 months ago
Online Estimation of Architectural Vulnerability Factor for Soft Errors
As CMOS technology scales and more transistors are packed on to the same chip, soft error reliability has become an increasingly important design issue for processors. Prior resea...
Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. ...
ICRA
1993
IEEE
118views Robotics» more  ICRA 1993»
15 years 1 months ago
Hip Implant Insertability Analysis: A Medical Instance of the Peg-In-Hole Problem
cavity Recent advan.cesin cementless hip replacement surgery have significantly improved the accuracy of bone cavity preparation and custom implant shape design. With the increased...
Leo Joskowicz, Russell H. Taylor