225 search results - page 6 / 45 » The Design and Optimization of SOC Test Solutions |
ICCD
2006
IEEE
15 years 6 months ago
2006
IEEE
— In this paper, we are proposing a core-based test methodology that utilizes the functional bus for test stimuli and response transportation. An efficient algorithm for the gen...
ETS
2010
IEEE
14 years 10 months ago
2010
IEEE
Testing of 3D stacked ICs (SICs) is becoming increasingly important in the semiconductor industry. In this paper, we address the problem of test architecture optimization for 3D s...
97
Voted
ISQED
2006
IEEE
15 years 3 months ago
2006
IEEE
— With advanced VLSI manufacturing technology in deep submicron (DSM) regime, we can integrate entire electronic systems on a single chip (SoC). Due to the complexity in SoC desi...
100
click to vote
DATE
2004
IEEE
15 years 1 months ago
2004
IEEE
For successful SoC design, efficient and scalable communication architecture is crucial. Some bus interconnects now provide configurable structures to meet this requirement of an ...
ASPDAC
2007
ACM
15 years 1 months ago
2007
ACM
Using multiple supply voltages on a SoC design is an efficient way to achieve low power. However, it may lead to a complex power network and a huge number of level shifters if we j...