Sciweavers

17409 search results - page 102 / 3482
» The Design and Performance of MedJava
Sort
View
ICCD
2005
IEEE
110views Hardware» more  ICCD 2005»
15 years 6 months ago
Implementing Caches in a 3D Technology for High Performance Processors
3D integration is an emergent technology that has the potential to greatly increase device density while simultaneously providing faster on-chip communication. 3D fabrication invo...
Kiran Puttaswamy, Gabriel H. Loh
CHI
2010
ACM
15 years 4 months ago
Characterizing debate performance via aggregated twitter sentiment
Television broadcasters are beginning to combine social micro-blogging systems such as Twitter with television to create social video experiences around events. We looked at one s...
Nicholas Diakopoulos, David A. Shamma
ICPP
2009
IEEE
15 years 4 months ago
Investigating High Performance RMA Interfaces for the MPI-3 Standard
—The MPI-2 Standard, released in 1997, defined an interface for one-sided communication, also known as remote memory access (RMA). It was designed with the goal that it should p...
Vinod Tipparaju, William Gropp, Hubert Ritzdorf, R...
DATE
2003
IEEE
103views Hardware» more  DATE 2003»
15 years 3 months ago
Reduced Delay Uncertainty in High Performance Clock Distribution Networks
The design of clock distribution networks in synchronous digital systems presents enormous challenges. Controlling the clock signal delay in the presence of various noise sources,...
Dimitrios Velenis, Marios C. Papaefthymiou, Eby G....
MICRO
2003
IEEE
152views Hardware» more  MICRO 2003»
15 years 3 months ago
A Systematic Methodology to Compute the Architectural Vulnerability Factors for a High-Performance Microprocessor
Single-event upsets from particle strikes have become a key challenge in microprocessor design. Techniques to deal with these transient faults exist, but come at a cost. Designers...
Shubhendu S. Mukherjee, Christopher T. Weaver, Joe...