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ICMCS
2005
IEEE
104views Multimedia» more  ICMCS 2005»
15 years 3 months ago
A High-Performance Memory-Efficient Architecture of the Bit-Plane Coder in JPEG 2000
The paper presents a high-performance architecture of the bit-plane coder for the embedded block coding algorithm in JPEG 2000. The architecture adopts a pipeline structure and is...
Grzegorz Pastuszak
HPDC
2000
IEEE
15 years 2 months ago
Flexible High-Performance Access to Distributed Storage Resources
We describe a software architecture for storage services in computational grid environments. Based upon a lightweight message-passing paradigm, the architecture enables the provis...
Craig J. Patten, Kenneth A. Hawick
ISPD
2000
ACM
124views Hardware» more  ISPD 2000»
15 years 2 months ago
A performance optimization method by gate sizing using statistical static timing analysis
We propose a gate resizing method for delay and power optimization that is based on statistical static timing analysis. Our method focuses on the component of timing uncertainties...
Masanori Hashimoto, Hidetoshi Onodera
CHI
2003
ACM
15 years 10 months ago
With similar visual angles, larger displays improve spatial performance
Large wall-sized displays are becoming prevalent. Although researchers have articulated qualitative benefits of group work on large displays, little work has been done to quantify...
Desney S. Tan, Darren Gergle, Peter Scupelli, Rand...
TRIDENTCOM
2008
IEEE
15 years 4 months ago
Performance analysis of a lightweight NEMO implementation for low-end devices
IETF Network Mobility (NEMO) Basic Support Protocol is an IP mobility management protocol designed to provide seamless IP mobility to complete networks. This protocol is of crucia...
J. L. Almodovar, Antonio de la Oliva, C. Lazo Ram,...