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» The Design and Performance of MedJava
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HPCA
2008
IEEE
15 years 10 months ago
Performance and power optimization through data compression in Network-on-Chip architectures
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicop...
HICSS
2007
IEEE
100views Biometrics» more  HICSS 2007»
15 years 4 months ago
Performance Analysis of a Middleware Demultiplexing Pattern
A key enabler of the recently adopted, assemblycentric development approach for distributed real-time software systems is QoS-enabled middleware, which provides reusable building ...
U. Praphamontripong, Swapna S. Gokhale, Aniruddha ...
MICRO
2005
IEEE
144views Hardware» more  MICRO 2005»
15 years 3 months ago
A Dynamic Compilation Framework for Controlling Microprocessor Energy and Performance
Dynamic voltage and frequency scaling (DVFS) is an effective technique for controlling microprocessor energy and performance. Existing DVFS techniques are primarily based on hardw...
Qiang Wu, Margaret Martonosi, Douglas W. Clark, Vi...
CODES
2009
IEEE
15 years 2 months ago
Native MPSoC co-simulation environment for software performance estimation
Performance estimation of Multi-Processor System-On-Chip (MPa high abstraction level is required in order to perform early architecture exploration and accurate design validations...
Patrice Gerin, Mian Muhammad Hamayun, Fréd&...
SIGSOFT
2007
ACM
15 years 10 months ago
CTG: a connectivity trace generator for testing the performance of opportunistic mobile systems
The testing of the performance of opportunistic communication protocols and applications is usually done through simulation as i) deployments are expensive and should be left to t...
Roberta Calegari, Mirco Musolesi, Franco Raimondi,...