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SIGMETRICS
2004
ACM
103views Hardware» more  SIGMETRICS 2004»
15 years 3 months ago
Myths and realities: the performance impact of garbage collection
This paper explores and quantifies garbage collection behavior for three whole heap collectors and generational counterparts: copying semi-space, mark-sweep, and reference counti...
Stephen M. Blackburn, Perry Cheng, Kathryn S. McKi...
ISCA
2003
IEEE
104views Hardware» more  ISCA 2003»
15 years 3 months ago
Token Coherence: Decoupling Performance and Correctness
Many future shared-memory multiprocessor servers will both target commercial workloads and use highly-integrated “glueless” designs. Implementing low-latency cache coherence i...
Milo M. K. Martin, Mark D. Hill, David A. Wood
CLUSTER
2002
IEEE
15 years 2 months ago
High Performance User Level Sockets over Gigabit Ethernet
While a number of User-Level Protocols have been developed to reduce the gap between the performance capabilities of the physical network and the performance actually available, a...
Pavan Balaji, Piyush Shivam, Pete Wyckoff, Dhabale...
MSWIM
2009
ACM
15 years 2 months ago
Modeling and performance evaluation of transmission control protocol over cognitive radio ad hoc networks
Cognitive Radio (CR) technology constitutes a new paradigm to provide additional spectrum utilization opportunities in wireless ad hoc networks. Recent research in this field has ...
Marco Di Felice, Kaushik Roy Chowdhury, Luciano Bo...
TVLSI
2010
14 years 4 months ago
C-Pack: A High-Performance Microprocessor Cache Compression Algorithm
Microprocessor designers have been torn between tight constraints on the amount of on-chip cache memory and the high latency of off-chip memory, such as dynamic random access memor...
Xi Chen, Lei Yang, Robert P. Dick, Li Shang, Haris...