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MICRO
2000
IEEE
68views Hardware» more  MICRO 2000»
15 years 8 months ago
Efficient checker processor design
The design and implementation of a modern microprocessor creates many reliability challenges. Designers must verify the correctness of large complex systems and construct implemen...
Saugata Chatterjee, Christopher T. Weaver, Todd M....
DAC
2003
ACM
16 years 4 months ago
Design flow for HW / SW acceleration transparency in the thumbpod secure embedded system
This paper describes a case study and design flow of a secure embedded system called ThumbPod, which uses cryptographic and biometric signal processing acceleration. It presents t...
David Hwang, Bo-Cheng Lai, Patrick Schaumont, Kazu...
ICCD
2007
IEEE
225views Hardware» more  ICCD 2007»
16 years 20 days ago
Fine grain 3D integration for microarchitecture design through cube packing exploration
Most previous 3D IC research focused on “stacking” traditional 2D silicon layers, so the interconnect reduction is limited to interblock delays. In this paper, we propose tech...
Yongxiang Liu, Yuchun Ma, Eren Kursun, Glenn Reinm...
147
Voted
SAMOS
2009
Springer
15 years 10 months ago
Visualization of Computer Architecture Simulation Data for System-Level Design Space Exploration
System-level computer architecture simulations create large volumes of simulation data to explore alternative architectural solutions. Interpreting and drawing conclusions from thi...
Toktam Taghavi, Mark Thompson, Andy D. Pimentel
FPGA
2010
ACM
191views FPGA» more  FPGA 2010»
15 years 10 months ago
Voter insertion algorithms for FPGA designs using triple modular redundancy
Triple Modular Redundancy (TMR) is a common reliability technique for mitigating single event upsets (SEUs) in FPGA designs operating in radiation environments. For FPGA systems t...
Jonathan M. Johnson, Michael J. Wirthlin