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DATE
2006
IEEE
102views Hardware» more  DATE 2006»
15 years 10 months ago
A systematic IP and bus subsystem modeling for platform-based system design
The topic on platform-based system modeling has received a great deal of attention today. One of the important tasks that significantly affect the effectiveness and efficiency of ...
Junhyung Um, Woo-Cheol Kwon, Sungpack Hong, Young-...
CAIP
2005
Springer
117views Image Analysis» more  CAIP 2005»
15 years 9 months ago
Design of Statistical Measures for the Assessment of Image Segmentation Schemes
Image segmentation is discussed for years in numerous papers, but assessing its quality is mainly dealt with in recent works. Quality assessment is a primary concern for anyone wor...
Marc Van Droogenbroeck, Olivier Barnich
ISPA
2004
Springer
15 years 9 months ago
A Fault Tolerance Protocol for Uploads: Design and Evaluation
This paper investigates fault tolerance issues in Bistro, a wide area upload architecture. In Bistro, clients first upload their data to intermediaries, known as bistros. A destin...
Leslie Cheung, Cheng-Fu Chou, Leana Golubchik, Yan...
ECRTS
2009
IEEE
15 years 1 months ago
On the Design and Implementation of a Cache-Aware Multicore Real-Time Scheduler
Multicore architectures, which have multiple processing units on a single chip, have been adopted by most chip manufacturers. Most such chips contain on-chip caches that are share...
John M. Calandrino, James H. Anderson
TSP
2010
14 years 10 months ago
Zero-forcing DFE transceiver design over slowly time-varying MIMO channels using ST-GTD
This paper considers the optimization of transceivers with decision feedback equalizers (DFE) for slowly time-varying memoryless multi-input multi-output (MIMO) channels. The data ...
Chih-Hao Liu, Palghat P. Vaidyanathan