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GECCO
2005
Springer
128views Optimization» more  GECCO 2005»
15 years 9 months ago
Fractional dynamic fitness functions for GA-based circuit design
This paper proposes and analyses the performance of a Genetic Algorithm (GA) using two new concepts, namely a static fitness function including a discontinuity measure and a fract...
Cecília Reis, José António Te...
DFT
2003
IEEE
117views VLSI» more  DFT 2003»
15 years 9 months ago
Fault Tolerant Design of Combinational and Sequential Logic Based on a Parity Check Code
We describe a method for designing fault tolerant circuits based on an extension of a Concurrent Error Detection (CED) technique. The proposed extension combines parity check code...
Sobeeh Almukhaizim, Yiorgos Makris
IESS
2009
Springer
131views Hardware» more  IESS 2009»
15 years 8 months ago
A Hybrid Hardware and Software Component Architecture for Embedded System Design
Abstract. Embedded systems are increasing in complexity, while several metrics such as time-to-market, reliability, safety and performance should be considered during the design of...
Hugo Marcondes, Antônio Augusto Fröhlic...
ASPDAC
2000
ACM
83views Hardware» more  ASPDAC 2000»
15 years 8 months ago
Low-power design of sequential circuits using a quasi-synchronous derived clock
– This paper presents a novel circuit design technique to reduce the power dissipation in sequential circuits by generating a quasi-synchronous derived clock from the master cloc...
Xunwei Wu, Jian Wei, Massoud Pedram, Qing Wu
132
Voted
DATE
1999
IEEE
123views Hardware» more  DATE 1999»
15 years 8 months ago
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs
This paper reports a formal methodology for verifying a broad class of synthesized register-transfer-level (RTL) designs by accommodating various register allocation/optimization ...
Nazanin Mansouri, Ranga Vemuri