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ISQED
2005
IEEE
125views Hardware» more  ISQED 2005»
15 years 9 months ago
A New Method for Design of Robust Digital Circuits
As technology continues to scale beyond 100nm, there is a significant increase in performance uncertainty of CMOS logic due to process and environmental variations. Traditional c...
Dinesh Patil, Sunghee Yun, Seung-Jean Kim, Alvin C...
IV
2005
IEEE
149views Visualization» more  IV 2005»
15 years 9 months ago
Visualisation Techniques for Users and Designers of Layout Algorithms
Visualisation systems consisting of a set of components through which data and interaction commands flow have been explored by a number of researchers. Such hybrid and multistage ...
Greg Ross, Alistair Morrison, Matthew Chalmers
CF
2004
ACM
15 years 9 months ago
Designing and testing fault-tolerant techniques for SRAM-based FPGAs
This paper discusses fault-tolerant techniques for SRAM-based FPGAs. These techniques can be based on circuit level modifications, with obvious modifications in the programmable a...
Fernanda Lima Kastensmidt, Gustavo Neuberger, Luig...
TSE
1998
128views more  TSE 1998»
15 years 3 months ago
Modeling and Evaluating Design Alternatives for an On-Line Instrumentation System: A Case Study
—This paper demonstrates the use of a model-based evaluation approach for instrumentation systems (ISs). The overall objective of this study is to provide early feedback to tool ...
Abdul Waheed, Diane T. Rover, Jeffrey K. Hollingsw...
ASPDAC
2010
ACM
150views Hardware» more  ASPDAC 2010»
15 years 2 months ago
Post-silicon debugging for multi-core designs
Escaped errors in released silicon are growing in number due to the increasing complexity of modern processor designs and shrinking production schedules. Worsening the problem are ...
Valeria Bertacco