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DAC
2010
ACM
15 years 7 months ago
TSV stress aware timing analysis with applications to 3D-IC layout optimization
As the geometry shrinking faces severe limitations, 3D wafer stacking with through silicon via (TSV) has gained interest for future SOC integration. Since TSV fill material and s...
Jae-Seok Yang, Krit Athikulwongse, Young-Joon Lee,...
114
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GLOBECOM
2007
IEEE
15 years 7 months ago
Complex Nakagami Channel Simulator with Accurate Phase and Auto-Correlation Properties
Accurate and systematic channel simulation technique is critical for performance verification of digital transceiver design over wireless channels. Despite the abundant results on ...
Yao Ma, Dongbo Zhang
ICC
2007
IEEE
139views Communications» more  ICC 2007»
15 years 7 months ago
Comparison of Protection Mechanisms: Capacity Efficiency and Recovery Time
High efficiency in capacity utilization and fast restoration are two primary goals of survivable design in optical networks. Shared backup path protection has been shown to be effi...
Wensheng He, Arun K. Somani
ICC
2007
IEEE
101views Communications» more  ICC 2007»
15 years 7 months ago
On the Fundamentally Asynchronous Nature of Interference in Cooperative Base Station Systems
Cooperative transmission by base stations can significantly improve the spectral efficiency of multiuser, multi-cell multiple input multiple output systems. We show that in such s...
Hongyuan Zhang, Neelesh B. Mehta, Andreas F. Molis...
GLVLSI
2009
IEEE
126views VLSI» more  GLVLSI 2009»
15 years 7 months ago
An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs
Recent technology mappers for LUT based FPGAs employ cut enumeration. Although many cuts are often needed to nd good network, enumerating all cuts with large size consumes run-tim...
Taiga Takata, Yusuke Matsunaga
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