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79
Voted
DAC
2000
ACM
15 years 10 months ago
2000
ACM
Latency insensitive design has been recently proposed in literature as a way to design complex digital systems, whose functional behavior is robust with respect to arbitrary varia...
82
Voted
ISCAS
2007
IEEE
15 years 4 months ago
2007
IEEE
-- In interconnect-dominated designs, the ability to minimize layout-induced parasitic effects is crucial for rapid design closure. Deep sub-micron effects and ubiquitous interfere...
ASYNC
2003
IEEE
15 years 3 months ago
2003
IEEE
Parameterized first-order models for throughput, energy, and bandwidth are presented in this paper. Models are developed for many common pipeline methodologies, including clocked...
71
Voted
DAC
2006
ACM
15 years 10 months ago
2006
ACM
Three-dimensional (3-D) integrated circuits have emerged as promising candidates to overcome the interconnect bottlenecks of nanometer scale designs. While they offer several othe...
89
Voted
IEEECIT
2005
IEEE
15 years 3 months ago
2005
IEEE
In embedded systems, performance and power are important inter-related issues that cannot be decoupled. Expensive and extensive simulations in a processor design space are usually...