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ICESS
2007
Springer
15 years 11 months ago
A Design Method for Heterogeneous Adders
The performance of existing adders varies widely in their speed and area requirements, which in turn sometimes makes designers pay a high cost in area especially when the delay req...
Jeong-Gun Lee, Jeong-A. Lee, Byeong-Seok Lee, Milo...
ACMICEC
2006
ACM
157views ECommerce» more  ACMICEC 2006»
15 years 11 months ago
Adaptive mechanism design: a metalearning approach
Auction mechanism design has traditionally been a largely analytic process, relying on assumptions such as fully rational bidders. In practice, however, bidders often exhibit unkn...
David Pardoe, Peter Stone, Maytal Saar-Tsechansky,...
ATS
2005
IEEE
98views Hardware» more  ATS 2005»
15 years 10 months ago
Untestable Multi-Cycle Path Delay Faults in Industrial Designs
The need for high-performance pipelined architectures has resulted in the adoption of latch based designs with multiple, interacting clocks. For such designs, time sharing across ...
Manan Syal, Michael S. Hsiao, Suriyaprakash Natara...
133
Voted
CODES
2005
IEEE
15 years 10 months ago
An architectural level design methodology for embedded face detection
Face detection and recognition research has attracted great attention in recent years. Automatic face detection has great potential in a large array of application areas, includin...
Vida Kianzad, Sankalita Saha, Jason Schlessman, Ga...
GLVLSI
2005
IEEE
85views VLSI» more  GLVLSI 2005»
15 years 10 months ago
VLSI CAD tool protection by birthmarking design solutions
Many techniques have been proposed in the past for the protection of VLSI design IPs (intellectual property). CAD tools and algorithms are intensively used in all phases of modern...
Lin Yuan, Gang Qu, Ankur Srivastava