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INFOCOM
2008
IEEE
15 years 11 months ago
Power Awareness in Network Design and Routing
Abstract—Exponential bandwidth scaling has been a fundamental driver of the growth and popularity of the Internet. However, increases in bandwidth have been accompanied by increa...
Joseph Chabarek, Joel Sommers, Paul Barford, Crist...
SOCC
2008
IEEE
169views Education» more  SOCC 2008»
15 years 11 months ago
A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies
— Lowering supply voltage is an effective technique for power reduction in memory design, however traditional memory cell design fails to operate, as shown in [3], [10], at ultra...
Jawar Singh, Jimson Mathew, Dhiraj K. Pradhan, Sar...
DATE
2007
IEEE
124views Hardware» more  DATE 2007»
15 years 11 months ago
Worst-case design and margin for embedded SRAM
An important aspect of Design for Yield for embedded SRAM is identifying the expected worst case behavior in order to guarantee that sufficient design margin is present. Previousl...
Robert C. Aitken, Sachin Idgunji
ICC
2007
IEEE
15 years 11 months ago
MIMO LMMSE Transceiver Design with Imperfect CSI at Both Ends
— This paper presents a new result on minimum total mean squared error (MSE) joint transceiver design for multiple-input multiple-output (MIMO) systems, with imperfect channel st...
Minhua Ding, Steven D. Blostein
ISCAS
2007
IEEE
106views Hardware» more  ISCAS 2007»
15 years 11 months ago
Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit Design
—Two probabilistic-based models, namely the Ensemble-Dependent Matrix model [1][3] and the Markov Random Field model [2], have been proposed to deal with faults in nanoscale syst...
Huifei Rao, Jie Chen, Changhong Yu, Woon Tiong Ang...