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FPL
2009
Springer
145views Hardware» more  FPL 2009»
15 years 9 months ago
Run-time Partial Reconfiguration speed investigation and architectural design space exploration
Run-time Partial Reconfiguration (PR) speed is significant in applications especially when fast IP core switching is required. In this paper, we propose to use Direct Memory Acce...
Ming Liu, Wolfgang Kuehn, Zhonghai Lu, Axel Jantsc...
CODES
2000
IEEE
15 years 9 months ago
ASDEN: a comprehensive design framework vision for automotive electronic control systems
The automotive electronics industry is experiencing an era of unprecedented growth. Driven by emissions and safety legislation, fuel economy constraints, cost constraints, and cus...
Deborah Wilson, Daniel Dayton, R. Todd Hansell
INFOVIS
1999
IEEE
15 years 9 months ago
Domain Analysis: A Technique to Design a User-Centered Visualization Framework
Domain Analysis for Data Visualization (DADV) is a technique to use when investigating a domain where data visualizations are going to be designed and added to existing software s...
Octavio Juarez Espinosa, Chris Hendrickson, James ...
149
Voted
TIP
1998
129views more  TIP 1998»
15 years 4 months ago
Minimax partial distortion competitive learning for optimal codebook design
— The design of the optimal codebook for a given codebook size and input source is a challenging puzzle that remains to be solved. The key problem in optimal codebook design is h...
Ce Zhu, Lai-Man Po
134
Voted
WCNC
2010
IEEE
15 years 3 months ago
Robust Relay Precoder Design for MIMO-Relay Networks
Abstract—In this paper, we consider a robust design of MIMOrelay precoder and receive filter for the destination nodes in a non-regenerative multiple-input multiple-output (MIMO...
P. Ubaidulla, Ananthanarayanan Chockalingam