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ICECCS
2002
IEEE
93views Hardware» more  ICECCS 2002»
15 years 11 months ago
Mnemosyne: Designing and Implementing Network Short-Term Memory
Network traffic logs play an important role in incident analysis. With the increasing throughput of network links, maintaining a complete log of all network activity has become a...
Giovanni Vigna, Andrew Mitchel
GECCO
2010
Springer
189views Optimization» more  GECCO 2010»
15 years 11 months ago
Knowledge mining with genetic programming methods for variable selection in flavor design
This paper presents a novel approach for knowledge mining from a sparse and repeated measures dataset. Genetic programming based symbolic regression is employed to generate multip...
Katya Vladislavleva, Kalyan Veeramachaneni, Matt B...
FPL
2009
Springer
99views Hardware» more  FPL 2009»
15 years 10 months ago
Exploiting fast carry-chains of FPGAs for designing compressor trees
Fast carry chains featuring dedicated adder circuitry is a distinctive feature of modern FPGAs. The carry chains bypass the general routing network and are embedded in the logic b...
Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
FPGA
2001
ACM
145views FPGA» more  FPGA 2001»
15 years 10 months ago
Simultaneous logic decomposition with technology mapping in FPGA designs
Conventional technology mapping algorithms for SRAM-based Field Programmable Gate Arrays (FPGAs) are normally carried out on a fixed logic decomposition of a circuit. The impact o...
Gang Chen, Jason Cong
ASPDAC
2000
ACM
104views Hardware» more  ASPDAC 2000»
15 years 10 months ago
Design of digital neural cell scheduler for intelligent IB-ATM switch
— We present the architecture of the ATM banyan switch composed of pattern process and high-speed digital neural cell scheduler. An input buffer type ATM switch with a window-bas...
J.-K. Lee, Seung-Min Lee, Mike Myung-Ok Lee, D.-W....