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» The Design and Performance of MedJava
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VLSISP
2008
93views more  VLSISP 2008»
15 years 7 months ago
Performance and Energy Consumption Improvements in Microprocessor Systems Utilizing a Coprocessor Data-Path
The speedups and the energy reductions achieved in a generic single-chip microprocessor system by employing a high-performance data-path are presented. The data-path acts as a copr...
Michalis D. Galanis, Gregory Dimitroulakos, Costas...
ISLPED
2003
ACM
80views Hardware» more  ISLPED 2003»
16 years 10 days ago
Level conversion for dual-supply systems
Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective approach to reduce chip power. The optimal CVS design relies on a level converter (LC) im...
Fujio Ishihara, Farhana Sheikh, Borivoje Nikolic
ICPP
1987
IEEE
15 years 10 months ago
Performance of VLSI Engines for Lattice Computations
Abstract. We address the problem of designing and building efficient custom Vl.Sl-besed processors to do computations on large multi-dimensional lattices. The design tradeoffs for ...
Steven D. Kugelmass, Kenneth Steiglitz, Richard K....
GLOBECOM
2009
IEEE
15 years 10 months ago
Rateless Codes with Optimum Intermediate Performance
—In this paper, we design several degree distributions for rateless codes with optimum intermediate packet recovery rates. In rateless coding, the employed degree distribution si...
Ali Talari, Nazanin Rahnavard
CORR
2006
Springer
99views Education» more  CORR 2006»
15 years 7 months ago
Intermediate Performance of Rateless Codes
Abstract-- Fountain codes are designed so that all input symbols can be recovered from a slightly larger number of coded symbols, with high probability using an iterative decoder. ...
Sujay Sanghavi