The speedups and the energy reductions achieved in a generic single-chip microprocessor system by employing a high-performance data-path are presented. The data-path acts as a copr...
Michalis D. Galanis, Gregory Dimitroulakos, Costas...
Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective approach to reduce chip power. The optimal CVS design relies on a level converter (LC) im...
Abstract. We address the problem of designing and building efficient custom Vl.Sl-besed processors to do computations on large multi-dimensional lattices. The design tradeoffs for ...
Steven D. Kugelmass, Kenneth Steiglitz, Richard K....
—In this paper, we design several degree distributions for rateless codes with optimum intermediate packet recovery rates. In rateless coding, the employed degree distribution si...
Abstract-- Fountain codes are designed so that all input symbols can be recovered from a slightly larger number of coded symbols, with high probability using an iterative decoder. ...