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ISCA
1997
IEEE
103views Hardware» more  ISCA 1997»
15 years 11 months ago
Designing High Bandwidth On-Chip Caches
In this paper we evaluate the performance of high bandwidth caches that employ multiple ports, multiple cycle hit times, on-chip DRAM, and a line buffer to find the organization t...
Kenneth M. Wilson, Kunle Olukotun
DAC
2007
ACM
16 years 8 months ago
Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization
Power gating is one of the most effective ways to reduce leakage power. In this paper, we introduce a new relationship among Maximum Instantaneous Current, IR drops and sleep tran...
De-Shiuan Chiou, Da-Cheng Juan, Yu-Ting Chen, Shih...
174
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DAC
2007
ACM
16 years 8 months ago
Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift
Statistical behavior of device leakage and threshold voltage shows a strong width dependency under microscopic random dopant fluctuation. Leakage estimation using the conventional...
Jie Gu, Sachin S. Sapatnekar, Chris H. Kim
DATE
2009
IEEE
89views Hardware» more  DATE 2009»
16 years 2 months ago
Exploiting clock skew scheduling for FPGA
- Clock skew scheduling (CSS) is an effective technique to optimize clock period of sequential designs. However, these techniques are not effective in the presence of certain desig...
Sungmin Bae, Prasanth Mangalagiri, Narayanan Vijay...
ALDT
2009
Springer
172views Algorithms» more  ALDT 2009»
16 years 2 months ago
On Multi-dimensional Envy-Free Mechanisms
Traditional performance analysis of approximation algorithms considers overall performance, while economic fairness analysis focuses on the individual performance each user receiv...
Ahuva Mu'alem