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DAC
2012
ACM
13 years 10 months ago
ComPLx: A Competitive Primal-dual Lagrange Optimization for Global Placement
We develop a projected-subgradient primal-dual Lagrange optimization for global placement, that can be instantiated with a variety of interconnect models. It decomposes the origin...
Myung-Chul Kim, Igor L. Markov
200
Voted
DAC
2005
ACM
16 years 8 months ago
A low latency router supporting adaptivity for on-chip interconnects
The increased deployment of System-on-Chip designs has drawn attention to the limitations of on-chip interconnects. As a potential solution to these limitations, Networks-on -Chip...
Jongman Kim, Dongkook Park, Theo Theocharides, Nar...
DAC
2006
ACM
16 years 8 months ago
Multiprocessor system-on-chip data reuse analysis for exploring customized memory hierarchies
The increasing use of Multiprocessor Systems-on-Chip (MPSoCs) for high performance demands of embedded applications results in high power dissipation. The memory subsystem is a la...
Ilya Issenin, Erik Brockmeyer, Bart Durinck, Nikil...
DAC
2006
ACM
16 years 8 months ago
Optimal simultaneous mapping and clustering for FPGA delay optimization
Both technology mapping and circuit clustering have a large impact on FPGA designs in terms of circuit performance, area, and power dissipation. Existing FPGA design flows carry o...
Joey Y. Lin, Deming Chen, Jason Cong
206
Voted
DATE
2002
IEEE
83views Hardware» more  DATE 2002»
16 years 13 days ago
Memory System Connectivity Exploration
In programmable embedded systems, the memory subsystem represents a major cost, performance and power bottleneck. To optimize the system for such different goals, the designer wou...
Peter Grun, Nikil D. Dutt, Alexandru Nicolau