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DATE
2007
IEEE
74views Hardware» more  DATE 2007»
15 years 4 months ago
Joint consideration of fault-tolerance, energy-efficiency and performance in on-chip networks
High reliability against noise, low energy consumption and high performance are key objectives in the design of on-chip networks. Recently some researchers have considered the var...
Alireza Ejlali, Bashir M. Al-Hashimi, Paul M. Rosi...
ICC
2007
IEEE
140views Communications» more  ICC 2007»
15 years 4 months ago
Performance Analysis for Overlay Multicast on Tree and M-D Mesh Topologies
— Without the multicast support from the underlying networks, overlay multicast has the advantage of implementing inter-domain multicast communications. Usually, overlay multicas...
Wanqing Tu
WOSP
2004
ACM
15 years 3 months ago
Analysing UML 2.0 activity diagrams in the software performance engineering process
In this paper we present an original method of analysing the newlyrevised UML2.0 activity diagrams. Our analysis method builds on our formal interpretation of these diagrams with ...
C. Canevet, Stephen Gilmore, Jane Hillston, Le&ium...
ICASSP
2011
IEEE
14 years 1 months ago
Performance analysis of a randomly spaced wireless microphone array
A randomly distributed microphone array is considered in this work. In many applications exact design of the array is impractical. The performance of these arrays, characterized b...
Shmulik Markovich Golan, Sharon Gannot, Israel Coh...
ICCAD
2001
IEEE
102views Hardware» more  ICCAD 2001»
15 years 6 months ago
Simulation-Based Automatic Generation of Signomial and Posynomial Performance Models for Analog Integrated Circuit Sizing
This paper presents a method to automatically generate posynomial response surface models for the performance parameters of analog integrated circuits. The posynomial models enabl...
Walter Daems, Georges G. E. Gielen, Willy M. C. Sa...