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CLUSTER
2006
IEEE
15 years 3 months ago
Designing High Performance and Scalable MPI Intra-node Communication Support for Clusters
As new processor and memory architectures advance, clusters start to be built from larger SMP systems, which makes MPI intra-node communication a critical issue in high performanc...
Lei Chai, Albert Hartono, Dhabaleswar K. Panda
CODES
2006
IEEE
15 years 3 months ago
A bus architecture for crosstalk elimination in high performance processor design
In deep sub-micron technology, the crosstalk effect between adjacent wires has become an important issue, especially between long on-chip buses. This effect leads to the increas...
Wen-Wen Hsieh, Po-Yuan Chen, TingTing Hwang
TSMC
2002
80views more  TSMC 2002»
14 years 9 months ago
Performance metric alerting: a new design approach for complex alerting problems
Alerting systems and related decision-making automation are widely used to enhance the safety and capability of controlled processes across many applications. Traditional alerting ...
L. C. Yang, J. K. Kuchar
TCAD
2010
154views more  TCAD 2010»
14 years 4 months ago
Performance-Driven Dual-Rail Routing Architecture for Structured ASIC Design Style
In recent years, structured application-specific integrated circuit (ASIC) design style has lessened the importance of mask cost. Multiple structured ASIC chip designs share the sa...
Fu-Wei Chen, Yi-Yu Liu
ISVLSI
2008
IEEE
143views VLSI» more  ISVLSI 2008»
15 years 4 months ago
BTB Access Filtering: A Low Energy and High Performance Design
Powerful branch predictors along with a large branch target buffer (BTB) are employed in superscalar processors for instruction-level parallelism exploitation. However, the large ...
Shuai Wang, Jie Hu, Sotirios G. Ziavras