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» The Design and Performance of a Conflict-Avoiding Cache
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MICRO
2009
IEEE
207views Hardware» more  MICRO 2009»
15 years 6 months ago
Extending the effectiveness of 3D-stacked DRAM caches with an adaptive multi-queue policy
3D-integration is a promising technology to help combat the “Memory Wall” in future multi-core processors. Past work has considered using 3D-stacked DRAM as a large last-level...
Gabriel H. Loh
HPCA
2008
IEEE
16 years 5 days ago
Performance and power optimization through data compression in Network-on-Chip architectures
The trend towards integrating multiple cores on the same die has accentuated the need for larger on-chip caches. Such large caches are constructed as a multitude of smaller cache ...
Reetuparna Das, Asit K. Mishra, Chrysostomos Nicop...
EUROSYS
2009
ACM
15 years 9 months ago
Improving the responsiveness of internet services with automatic cache placement
The backends of today’s Internet services rely heavily on caching at various layers both to provide faster service to common requests and to reduce load on back-end components. ...
Alexander Rasmussen, Emre Kiciman, V. Benjamin Liv...
ACSAC
1999
IEEE
15 years 4 months ago
A Middleware Approach to Asynchronous and Backward Compatible Detection and Prevention of ARP Cache Poisoning
This paper discusses the Address Resolution Protocol (ARP) and the problem of ARP cache poisoning. ARP cache poisoning is the malicious act, by a host in a LAN, of introducing a s...
Mahesh V. Tripunitara, Partha Dutta
COMCOM
2002
120views more  COMCOM 2002»
14 years 11 months ago
An interactive video delivery and caching system using video summarization
With the advance of high-speed network technologies, the availability and popularity of streaming media content over the Internet has grown rapidly in recent years. The delivery a...
Sung-Ju Lee, Wei-Ying Ma, Bo Shen