867 search results - page 61 / 174 » The Design and Performance of a Conflict-Avoiding Cache |
INFOCOM
2009
IEEE
15 years 6 months ago
2009
IEEE
—Peer-assisted Video-on-Demand (VoD) systems have not only received substantial recent research attention, but also been implemented and deployed with success in large-scale real...
MICRO
2006
IEEE
15 years 5 months ago
2006
IEEE
Recently-proposed processor microarchitectures for high Memory Level Parallelism (MLP) promise substantial performance gains. Unfortunately, current cache hierarchies have Miss-Ha...
103
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MICRO
2007
IEEE
15 years 6 months ago
2007
IEEE
A significant part of future microprocessor real estate will be dedicated to L2 or L3 caches. These on-chip caches will heavily impact processor performance, power dissipation, a...
109
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MICRO
2003
IEEE
15 years 5 months ago
2003
IEEE
It is widely accepted that the disproportionate scaling of transistor and conventional on-chip interconnect performance presents a major barrier to future high performance systems...
114
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LCTRTS
2005
Springer
15 years 5 months ago
2005
Springer
Effective use of the memory hierarchy is critical for achieving high performance on embedded systems. We focus on the class of streaming applications, which is increasingly preval...