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» The Design and Performance of a Conflict-Avoiding Cache
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WSC
1997
15 years 1 months ago
Efficient Instruction Cache Simulation and Execution Profiling with a Threaded-Code Interpreter
We present an extension to an existing SPARC V8 instruction set simulator, SimICS, to support accurate profiling of branches and instruction cache misses. SimICS had previously su...
Peter S. Magnusson
ISLPED
2005
ACM
101views Hardware» more  ISLPED 2005»
15 years 5 months ago
Energy-aware fetch mechanism: trace cache and BTB customization
1 A highly-efficient fetch unit is essential not only to obtain good performance but also to achieve energy efficiency. However, existing designs are inflexible and depending on pr...
Daniel Chaver, Miguel A. Rojas, Luis Piñuel...
SASP
2008
IEEE
164views Hardware» more  SASP 2008»
15 years 6 months ago
AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications
This paper proposes an energy efficient processor which can be used as a design alternative for the dynamic voltage scaling (DVS) processors in embedded system design. The proces...
Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishito...
HPCA
2000
IEEE
15 years 4 months ago
Impact of Chip-Level Integration on Performance of OLTP Workloads
With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. So...
Luiz André Barroso, Kourosh Gharachorloo, A...
DAC
2010
ACM
15 years 3 months ago
Off-chip memory bandwidth minimization through cache partitioning for multi-core platforms
We present a methodology for off-chip memory bandwidth minimization through application-driven L2 cache partitioning in multicore systems. A major challenge with multi-core system...
Chenjie Yu, Peter Petrov