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» The Design and Performance of a Conflict-Avoiding Cache
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ASPLOS
2008
ACM
15 years 1 months ago
Exploiting access semantics and program behavior to reduce snoop power in chip multiprocessors
Integrating more processor cores on-die has become the unanimous trend in the microprocessor industry. Most of the current research thrusts using chip multiprocessors (CMPs) as th...
Chinnakrishnan S. Ballapuram, Ahmad Sharif, Hsien-...
ICS
2009
Tsinghua U.
15 years 6 months ago
/scratch as a cache: rethinking HPC center scratch storage
To sustain emerging data-intensive scientific applications, High Performance Computing (HPC) centers invest a notable fraction of their operating budget on a specialized fast sto...
Henry M. Monti, Ali Raza Butt, Sudharshan S. Vazhk...
ISCAS
2006
IEEE
157views Hardware» more  ISCAS 2006»
15 years 5 months ago
DCOS: cache embedded switch architecture for distributed shared memory multiprocessor SoCs
Abstract— Shared memory is a common inter-processor communication paradigm for on-chip multiprocessor SoC (MPSoC) platforms. The latency overhead of switch-based interconnection ...
Daewook Kim, Manho Kim, Gerald E. Sobelman
AINA
2008
IEEE
15 years 6 months ago
Dynamic Cache Invalidation Scheme in IR-Based Wireless Environments
Traditional cache invalidation schemes are not suitable to be employed in wireless environments due to the affections of mobility, energy consumption, and limited bandwidth. Cache ...
Yeim-Kuan Chang, Yi-Wei Ting, Tai-Hong Lin
HPCA
2009
IEEE
16 years 11 days ago
A first-order fine-grained multithreaded throughput model
Analytical modeling is an alternative to detailed performance simulation with the potential to shorten the development cycle and provide additional insights. This paper proposes a...
Xi E. Chen, Tor M. Aamodt