867 search results - page 75 / 174 » The Design and Performance of a Conflict-Avoiding Cache |
112
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EUROPAR
2004
Springer
15 years 5 months ago
2004
Springer
We present hoc: a fast, scalable object repository providing programmers with a general storage module. hoc may be used to implement DSMs as well as distributed cache subsystems. h...
188
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ASPLOS
2009
ACM
16 years 15 days ago
2009
ACM
Modern processors use branch target buffers (BTBs) to predict the target address of branches such that they can fetch ahead in the instruction stream increasing concurrency and pe...
IEEEPACT
2003
IEEE
15 years 5 months ago
2003
IEEE
Recent research shows that the high occupancy of Coherence Controllers (CCs) is a major performance bottleneck in scalable shared-memory multiprocessors. In this paper, we propose...
109
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DAC
2011
ACM
13 years 11 months ago
2011
ACM
As transistor dimensions continue to scale deep into the nanometer regime, silicon reliability is becoming a chief concern. At the same time, transistor counts are scaling up, ena...
123
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ISCA
1995
IEEE
15 years 3 months ago
1995
IEEE
For many programs, especially integer codes, untolerated load instruction latencies account for a significant portion of total execution time. In this paper, we present the desig...